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1 of 16 rev : 121306 note: some revisions of this device may incor porate deviations from published specifications known as erra ta. multiple revisions of any device may be simultaneously available through various sales channel s. for information about device errata, click here: www.maxim-ic.com/errata . features integrated nv sram, real-time clock, crystal, power-fail control circuit, and lithium energy source clock registers are accessed identically to the static ram. these registers reside in the eight top ram locations. century byte register totally nonvolatile wi th over 10 years of operation in the absence of power bcd-coded century, year, month, date, day, hours, minutes, and seconds with automatic leap year compensation valid through 2099 low-battery-voltage level indicator flag power-fail write protection allows for 10% v cc power-supply tolerance lithium energy source is electrically disconnected to retain freshness until power is applied for the first time dip module only standard jedec bytewide 8k x 8 static ram pinout powercap module board only surface-mountable package for direct connection to powercap containing battery and crystal replaceable battery (powercap) power-on reset output pin-for-pin compatible with other densities of ds174xp timekeeping ram underwriters laboratory (ul) recognized to prevent charging of the internal lithium battery pin configurations ds1743/ds1743p y2k-compliant, nonvolatile timekeeping rams www.maxim-ic.com v cc w e ce2 a 8 a 9 a 11 o e a 10 c e dq7 dq6 dq5 dq4 dq3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 n.c. a12 a7 a6 a5 a4 a3 a2 a1 a0 dq0 dq1 dq2 gnd 28 27 26 25 24 23 22 21 20 19 18 17 16 15 28-pin encapsulated package ( 28 pin 740 ) ds1743 1 n.c. 2 3 n.c. n.c. r s t v cc we oe ce dq7 dq6 dq5 dq4 dq3 dq2 dq1 dq0 gnd 4 5 6 7 8 9 10 11 12 13 14 15 16 17 n.c. n.c. 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 n.c. a 12 a 11 a 10 a 9 a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 34 n.c. x1 gnd v bat x2 34-pin powercap module board ( uses ds9034pcx powerca p) ds1743p top view
ds1743/ds1743p y2k-compliant, nonvolatile timekeeping rams 2 of 16 pin description pin pdip powercap name function 1 1, 2, 3, 31?34 n.c. no connection 2 30 a12 3 25 a7 4 24 a6 5 23 a5 6 22 a4 7 21 a3 8 20 a2 9 19 a1 10 18 a0 address input 11 16 dq0 12 15 dq1 13 14 dq2 data input/ output 14 17 gnd ground 15 13 dq3 16 12 dq4 17 11 dq5 18 10 dq6 19 9 dq7 data input/ output pin pdip powercap name function 20 8 ce chip enable, active low 21 28 a10 address input 22 7 oe output enable, active low 23 29 a11 24 27 a9 25 26 a8 address input 26 ? ce2 chip enable 2 27 6 we write enable, active low 28 5 v cc power-supply input ? 4 rst power-on reset output, active low ? x1, x2 crystal connection ? v bat battery connection
ds1743/ds1743p y2k-compliant, nonvolatile timekeeping rams 3 of 16 ordering information part temp range pin-package voltage (v) top mark** ds1743 -70 0c to +70c 28 edip module 5 ds1743-70 ds1743-85 0c to +70c 28 edip module 5 ds1743-85 ds1743-100 0c to +70c 28 edip module 5 ds1743-100 ds1743-100 ind -40c to +85c 28 edip module 5 ds1743-100-ind ds1743p-70 0c to +70c 34 powercap* 5 ds1743p-70 ds1743p-85 0c to +70c 34 powercap* 5 ds1743p-85 ds1743p-100 0c to +70c 34 powercap* 5 ds1743p-100 ds1743p-100ind -40c to +85c 34 powercap* 5 ds1743p-100 ind ds1743w-120 0c to +70c 28 edip module 3.3 ds1743w-120 ds1743w-120 ind -40c to +85c 28 edip module 3.3 ds1743w-120 ind ds1743w-150 0c to +70c 28 edip module 3.3 ds1743w-150 ds1743w-150 ind -40c to +85c 28 edip module 3.3 ds1743w-150 ind ds1743wp-120 0c to +70c 34 powercap* 3.3 ds1743wp-120 ds1743wp-120 ind -40c to +85c 34 powercap* 3.3 ds1743wp-120 ind ds1743-70+ 0c to +70c 28 edip module 5 ds1743-70 ds1743-85+ 0c to +70c 28 edip module 5 ds1743-85 ds1743-100+ 0c to +70c 28 edip module 5 ds1743-100 ds1743-100 ind+ -40c to +85c 28 edip module 5 ds1743-100-ind ds1743p-70+ 0c to +70c 34 powercap* 5 ds1743p-70 ds1743p-85+ 0c to +70c 34 powercap* 5 ds1743p-85 ds1743p-100+ 0c to +70c 34 powercap* 5 ds1743p-100 ds1743p-100ind+ -40c to +85c 34 powercap* 5 ds1743p-100 ind ds1743w-120+ 0c to +70c 28 edip module 3.3 ds1743w-120 ds1743w-120 ind+ -40c to +85c 28 edip module 3.3 ds1743w-120 ind ds1743w-150+ 0c to +70c 28 edip module 3.3 ds1743w-150 ds1743w-150 ind+ -40c to +85c 28 edip module 3.3 ds1743w-150 ind ds1743wp-120+ 0c to +70c 34 powercap* 3.3 ds1743wp-120 ds1743wp-120 ind+ -40c to +85c 34 powercap* 3.3 ds1743wp-120 ind ds9034pcx 0c to +70c powercap ? ds9034pc ds90340i-pcx -40c to +85c powercap ind ? ds9034pci ds9034pcx+ 0c to +70c powercap ? ds9034pc ds90340i-pcx+ -40c to +85c powercap ind ? ds9034pci * ds9034pcx required (must be ordered separately). **a ?+? indicates lead-free. the top mark w ill include a ?+? symbol on lead-free devices. description the ds1743 is a full-function, year-2000-compliant (y 2kc), real-time clock/cal endar (rtc) and 8k x 8 nonvolatile static ram. user access to all registers within the ds1743 is accomplished with a bytewide interface as shown in figure 1. the rtc information a nd control bits reside in the eight uppermost ram locations. the rtc registers contain century, year, m onth, date, day, hours, minutes, and seconds data in 24-hour binary-coded decimal (bcd) format. corrections for the day of the month and leap year are made automatically. the rtc clock registers are double buffere d to avoid access of incorrect data that can occur during clock update cycles. the double-buffered system also prevents time loss as the timekeeping countdown continues unabated by access to time regist er data. the ds1743 also contains its own power- fail circuitry, which deselects the device when the v cc supply is in an out-of- tolerance condition. when v cc is above v pf , the device is fully accessible. when v cc is below v pf , the internal ce signal is forced
ds1743/ds1743p y2k-compliant, nonvolatile timekeeping rams 4 of 16 high, preventing any access. when v cc rises above v pf , access remains inhibited for t rec , allowing time for the system to stabilize. these features prevent loss of data from unpredictable system operation brought on by low v cc as errant access and update cycles are avoided. packages the ds1743 is available in two packages: the 28-pin dip and the 34-pin powercap module. the 28-pin dip-style module integrates the crystal, lithium ener gy source, and silicon all in one package. the 34-pin powercap module board is designed with contacts for connection to a separate powercap (ds9034pcx) that contains the crystal and battery. this design allows the powercap to be mounted on top of the ds1743p after the completion of the surface-mount pr ocess. mounting the powe rcap after the surface- mount process prevents damage to th e crystal and battery due to the high temperatures required for solder reflow. the powercap is keyed to prevent reverse insertion. the powercap module board and powercap are ordered separately and shipped in separate containers. the part number for the powercap is ds9034pcx. time and date operation the time and date information is obtained by reading the appropriate register bytes. table 2 shows the rtc registers. the time and date are set or initial ized by writing the appropriate register bytes. the contents of the time and date regi sters are in the bcd format. the da y-of-week register increments at midnight. values that correspond to the day of week ar e user-defined, but must be sequential (i.e., if 1 equals sunday, then 2 equals mond ay and so on). illogical time and date entries resu lt in undefined operation. clock operations-reading the clock while the double-buffered register st ructure reduces the chance of readi ng incorrect data, internal updates to the ds1743 clock registers should be halted before clock data is read to prevent reading of data in transition. however, halting the inte rnal clock register up dating process does not affect clock accuracy. updating is halted when a 1 is written into the read bit, bit 6 of the centu ry register (see table 2). as long as a 1 remains in that position, updating is halted. after a halt is issued, the regist ers reflect the count that is day, date, and time that was current at the moment the halt command was issued. however, the internal clock registers of the double-buffered system continue to update so that the clock accuracy is not affected by the access of data. all the ds1743 registers are updated simultaneously af ter the internal clock register updating process has been re-enabled. updating is with in a second after the read bit is written to 0. the read bit must be a zero for a minimum of 500 s to ensure the extern al registers are updated.
ds1743/ds1743p y2k-compliant, nonvolatile timekeeping rams 5 of 16 figure 1. block diagram table 1. truth table v cc ce ce2 oe we mode dq power v ih x x x deselect high-z standby x v il x x deselect high-z standby v il v ih x v il write data in active v il v ih v il v ih read data out active v cc > v pf v il v ih v ih v ih read high-z active v so < v cc < v pf x x x x deselect high-z cmos standby v cc ds1743/ds1743p y2k-compliant, nonvolatile timekeeping rams 6 of 16 clock accuracy (dip module) the ds1743 is guaranteed to k eep time accuracy to within 1 minute per month at +25 c. the rtc is calibrated at the factory by dallas semiconductor usi ng nonvolatile tuning elements, and does not require additional calibration. for this reason, methods of field clock calibration ar e not available and not necessary. the electrical environmen t also affects clock accuracy, so caution should be taken to place the rtc in the lowest-level emi section of the pc board layout. for additional information, please refer to application note 58: crys tal considerations with dallas real-time clocks . clock accuracy (powercap module) the ds1743 and ds9034pcx are each individually test ed for accuracy. once mounted together, the module will typically keep time accuracy to within 1.53 minutes per month (35ppm) at +25c. the electrical environment also affects clock accuracy, so caution should be taken to place the rtc in the lowest-level emi section of the pc board layo ut. for additional information, please refer to application note 58: crystal considerations with dallas real-time clocks . table 2. register map data address b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 function range 1fff 10 year year year 00?99 1ffe x x x 10 month month month 01?12 1ffd x x 10 date date date 01?31 1ffc bf ft x x x day day 01?07 1ffb x x 10 hour hour hour 00?23 1ffa x 10 minutes minutes minutes 00?59 1ff9 osc 10 seconds seconds seconds 00?59 1ff8 w r 10 century century control 00?39 osc = stop bit r = read bit ft = frequency test w = write bit x = see note below bf = battery flag note: all indicated ?x? bits must be set to ?0? when written to ensure proper clock operation. retrieving data from ram or clock the ds1743 is in the read mode whenever oe (output enable) is low, we (write enable) is high, and ce (chip enable) is low. the device ar chitecture allows ripple-th rough access to any of th e address locations in the nv sram. valid data will be av ailable at the dq pins within t aa after the last address input is stable, providing that the, ce and oe access times and states are satisfied. if ce , or oe access times and states are not met, valid data will be availabl e at the latter of chip enable access (t cea ) or at output enable access time (t cea ). the state of the data input/ output pins (dq) is controlled by ce and oe. if the outputs are activated before t aa , the data lines are driven to an intermediate state until t aa . if the address inputs are changed while ce and oe remain valid, output data will rema in valid for output data hold time (t oh ) but will then go indeterminate until the next address access.
ds1743/ds1743p y2k-compliant, nonvolatile timekeeping rams 7 of 16 writing data to ram or clock the ds1743 is in the write mode whenever we , and ce are in their active state. the start of a write is referenced to the latter occurring transition of we , on ce . the addresses must be held valid throughout the cycle. ce or we must return inactive for a minimum of t wr prior to the initiation of another read or write cycle. data in must be valid t ds prior to the end of write and remain valid for t dh afterward. in a typical application, the oe signal will be high during a write cycle. however, oe can be active provided that care is taken with the data bus to avoid bus contention. if oe is low prior to we transitioning low the data bus can become active with read data define d by the address inputs. a low transition on we will then disable the outputs t wez after we goes active. data-retention mode the 5v device is fully accessible and data can be written or read only when v cc is greater than v pf. however, when v cc is below the power-fail point, v pf , (point at which writ e protection occurs) the internal clock registers and sram are blocked from any access. at th is time (powercap only) the power- fail reset-output signal ( rst ) is driven active and remains active until v cc returns to nominal levels. when v cc falls below the battery switch point v so (battery supply level), device power is switched from the v cc in to the backup battery. rtc operation and sram data are maintained from the battery until v cc is returned to nominal levels. the 3.3v device is fully accessible and data can be written or read only when v cc is greater than v pf . when v cc falls below the power-fail point, v pf , access to the device is inhi bited. at this time the power- fail reset-output signal ( rst ) is driven active and remains active until v cc returns to nominal levels. if v pf is less than v so , the device power is switched from v cc to the backup supply (v bat ) when v cc drops below v pf . if v pf is greater than v so , the device power is switched from v cc to the backup supply (v bat ) when v cc drops below v so . rtc operation and sram data are maintained from the battery until v cc is returned to nominal levels. the rst (powercap only) signal is an ope n-drain output and requires a pullup resistor. except for rst , all control, data, and address si gnals must be powered down when v cc is powered down. battery longevity the ds1743 has a lithium power source that is designe d to provide energy for cl ock activity and clock and ram data retention when the v cc supply is not present. the capability of this internal power supply is sufficient to power the ds1743 continuously for the life of the equipm ent in which it is installed. for specification purposes, the life expectancy is 10 years at +25 c with the internal clock oscillator running in the absence of v cc power. each ds1743 is shipped from dalla s semiconductor with its lithium energy source disconnected, guaranteeing full energy capacity. when v cc is first applied at a level greater than v pf , the lithium energy source is enabled for battery backup operation. actual life expectancy of the ds1743 will be longer than 10 years since no lith ium battery energy is consumed when v cc is present. battery monitor the ds1743 constantly monito rs the battery voltage of the internal battery. the battery flag bit (bit 7) of the day register is used to indicat e the voltage level range of the battery. this bit is not writeable and should always be a 1 when read. if a 0 is ever presen t, an exhausted lithium ener gy source is indicated and both the contents of the rtc and ram are questionable.
ds1743/ds1743p y2k-compliant, nonvolatile timekeeping rams 8 of 16 absolute maximum ratings voltage range on any pin relative to ground????????????????????-0.3v to +6.0v operating temperature range??????? ???????????????????.-40c to +85c storage temperature range??????????? ????????????????.-40c to +85c soldering temperature (edip) (leads, 10 seconds)????????.???????????..?+260c soldering temperature????????????????..?.see j-std-020 specification (see note 8) this is a stress rating only and functional operation of the device at these or any ot her conditions above those indicated in t he operation sections of this specification is not implied. ex posure to absolute maximum rating conditions for extended periods of time may affect de vice reliability. operating range range temp range v cc commercial 0c to +70c 3.3v 10% or 5v 10% industrial -40 c to +85 c 3.3v 10% or 5v 10% recommended dc oper ating conditions (t a = over the operating range.) parameter symbol conditions min typ max units notes v cc = 5v 10% 2.2 v cc +0.3v v 1 logic 1 voltage all inputs v ih v cc = 3.3v 10% 2.0 v cc +0.3v v 1 v cc = 5v 10% -0.3 +0.8 v 1 logic 0 voltage all inputs v il v cc = 3.3v 10% -0.3 +0.6 v 1 dc electrical characteristics (5v) ( v cc = 5.0v 10%, t a = over the operating range.) parameter symbol min typ max units notes active supply current i cc 15 50 ma 2, 3 ttl standby current ( ce = v ih , ce2 = v il ) i cc1 1 3 ma 2, 3 cmos standby current ( ce v cc - 0.2v; ce2 = gnd + 0.2v) i cc2 1 3 ma 2, 3 input leakage current (any input) i il -1 +1 a output leakage current (any output) i ol -1 +1 a output logic 1 voltage (i out = -1.0ma) v oh 2.4 1 output logic 0 voltage (i out = 2.1ma) v ol1 0.4 1 write-protection voltage v pf 4.20 4.50 v 1 battery switchover voltage v so v bat 1, 4
ds1743/ds1743p y2k-compliant, nonvolatile timekeeping rams 9 of 16 dc electrical characteristics (3.3v) ( v cc = 3.3v 10% , t a = over the operating range.) parameter symbol min typ max units notes active supply current i cc 10 30 ma 2, 3 ttl standby current ( ce = v ih ) i cc1 0.7 2 ma 2, 3 cmos standby current ( ce v cc - 0.2v; ce2 = gnd + 0.2v) i cc2 0.7 2 ma 2, 3 input leakage current (any input) i il -1 +1 a output leakage current (any output) i ol -1 +1 a output logic 1 voltage (i out = -1.0ma) v oh 2.4 1 output logic 0 voltage (i out =2.1ma) v ol1 0.4 1 write-protection voltage v pf 2.75 2.97 v 1 battery switchover voltage v so v bat or v pf v 1, 4 ac characteristics?read cycle (5v) (v cc = 5.0v 10%, t a = over the operating range .) access 70ns 85ns 100ns parameter symbol min max min max min max units notes read cycle time t rc 70 85 100 ns address access time t aa 70 85 100 ns ce to ce2 to dq low-z t cel 5 5 5 ns 5 ce access time t cea 70 85 100 ns 5 ce2 access time t ce2a 80 95 105 ns 5 ce and ce2 data-off time t cez 25 30 35 ns oe to dq low-z t oel 5 5 5 ns oe access time t oea 35 45 55 ns oe data-off time t oez 25 30 35 ns output hold from address t oh 5 5 5 ns
ds1743/ds1743p y2k-compliant, nonvolatile timekeeping rams 10 of 16 ac characteristics?read cycle (3.3v) ( v cc = 3.3v 10% , t a = over the operating range.) access 120ns 150ns parameter symbol min max min max units notes read cycle time t rc 120 150 ns address access time t aa 120 150 ns ce and ce2 low to dq low-z t cel 5 5 ns 5 ce and ce2 access time t cea 120 150 ns 5 ce and ce2 data-off time t cez 40 50 ns 5 oe low to dq low-z t oel 5 5 ns oe access time t oea 100 130 ns oe data-off time t oez 35 35 ns output hold from address t oh 5 5 ns read cycle timing diagram
ds1743/ds1743p y2k-compliant, nonvolatile timekeeping rams 11 of 16 ac characteristics?write cycle (5v) (v cc = 5.0v 10%, t a = over the operating range.) access 70ns 85ns 100ns parameter symbol min max min max min max units notes write cycle time t wc 70 85 100 ns address setup time t as 0 0 0 ns 5 we pulse width t wew 50 65 70 ns ce pulse width t cew 60 70 75 ns 5 ce2 pulse width t ce2w 65 75 85 ns 5 data setup time t ds 30 35 40 ns 5 data hold time ce t dh 0 0 0 ns 5 data hold time ce2 t dh 8 8 8 ns 5 address hold time t ah 5 5 5 ns 5 we data-off time t wez 25 30 35 ns write recovery time t wr 10 10 10 ns ac characteristics?write cycle (3.3v) ( v cc = 3.3v 10% , t a = over the operating range.) access 120ns 150ns parameter symbol min max min max units notes write cycle time t wc 120 150 ns address setup time t as 0 0 ns 5 we pulse width t wew 100 130 ns ce and ce2 pulse width t cew 110 140 ns 5 data setup time t ds 80 90 ns 5 data hold time ce t dh 0 0 ns 5 data hold time ce2 t dh 10 10 ns 5 address hold time t ah 0 0 ns 5 we data-off time t wez 40 50 ns write recovery time t wr 10 10 ns
ds1743/ds1743p y2k-compliant, nonvolatile timekeeping rams 12 of 16 write cycle timing?wri te-enable controlled (see note 5) write cycle timing? ce /ce2-controlled (see note 5)
ds1743/ds1743p y2k-compliant, nonvolatile timekeeping rams 13 of 16 power-up/down char acteristics?5v (v cc = 5.0v 10%, t a = over the operating range.) parameter symbol min typ max units notes ce or we at v ih , ce2 at v il , before power-down t pd 0 s v cc fall time: v pf(max) to v pf(min) t f 300 s v cc fall time: v pf(min) to v so t fb 10 s v cc rise time: v pf(min) to v pf(max) t r 0 s power-up recover time t rec 35 ms expected data-retention time (oscillator on) t dr 10 years 6, 7 power-up/down timing (5v device)
ds1743/ds1743p y2k-compliant, nonvolatile timekeeping rams 14 of 16 power-up/down char acteristics?3.3v ( v cc = 3.3v 10% , t a = over the operating range.) parameter symbol min typ max units notes ce or we at v ih , before power-down t pd 0 s v cc fall time: v pf(max) to v pf(min) t f 300 s v cc rise time: v pf(min) to v pf(max) t r 0 s v pf to rst high t rec 35 ms expected data-retention time (oscillator on) t dr 10 years 6, 7 power-up/down waveform timing (3.3v device) capacitance (t a = +25 c) parameter symbol min typ max units notes capacitance on all input pins c in 7 pf capacitance on all output pins c o 10 pf
ds1743/ds1743p y2k-compliant, nonvolatile timekeeping rams 15 of 16 ac test conditions output load: 50 pf + 1ttl gate input pulse levels: 0 to 3.0v timing measurement reference levels: input: 1.5v output: 1.5v input pulse rise and fall times: 5ns notes: 1) voltages are referenced to ground. 2) typical values are at +25 c and nominal supplies. 3) outputs are open. 4) battery switchover occurs at the lower of either the battery terminal voltage or v pf . 5) the ce2 control signal functions the same as the ce signal except that the logic levels for active and inactive levels are opposite. if ce2 is used to terminate a wr ite, the ce2 data hold time (t dh ) applies. 6) data-retention time is at +25 c. 7) each ds1743 has a built-in switch that disconnects the lith ium source until v cc is first applied by the user. the expected t dr is defined for dip modules as a cu mulative time in the absence of v cc starting from the time power is first applied by the user. 8) rtc encapsulated dip modules (edip) can be successfully processed through conventional wave- soldering techniques as long as temperatures as long as temperature exposure to the lithium energy source contained within does not exceed +85 c. post-solder cleaning with water-washing techniques is acceptable, provided that ultrasonic vibration is not used. see the powercap package drawing for details regarding the powercap package.
ds1743/ds1743p y2k-compliant, nonvolatile timekeeping rams 16 of 16 maxim/dallas semiconductor cannot assume res ponsibility for use of any circuitry other than circuitry entirely embodied in a ma xim/dallas semiconductor product. no circuit patent licenses are implied. maxim/dallas semiconductor reserves the right to change the circuitry and specifications w ithout notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ? 2006 maxim integrated products the maxim logo is a registered trademark of maxim integrated pr oducts, inc. the dallas logo is a registered trademark of dallas semiconductor. package information for the latest package outline information, go to www.maxim-ic.com/dallaspackinfo . 28-pin 740 edip module document number: 56-g0002-001 32-pin powercap module document number: 56-g0003-001
ds1743 part number table english ? ? ?Z ? ??? what's new products solutions design appnotes support buy company members notes: 1. see the ds1743 quickview data sheet for further information on this product family or download the ds1743 full data sheet (pdf, 316kb). 2. other options and links for pu rchasing parts are listed at: http://www.maxim-ic.com/sales . 3. didn't find what you need? ask our applications engineers. expert assistance in finding parts, usually within one business day. 4. part number suffixes: t or t&r = tape and reel; + = rohs/lead-free ; # = rohs/lead-exempt. more: see full data sheet or part naming conventions . 5. * some packages have variations, list ed on the drawing. "pkgcode/variation" tells which variation the product uses. part number free sample buy direct package: type pins size drawing code/var * temp rohs/lead-free? materials analysis ds1743-85+ sample buy mod;28 pin;600 dwg: 56-g0002-001a (pdf) use pkgcode/vari ation: mdf28+2 * 0c to +70c rohs/lead-free: yes materials analysis ds1743-85ind+ buy mod;28 pin;600 dwg: 56-g0002-001a (pdf) use pkgcode/vari ation: mdf28+2 * -40c to +85c rohs/lead-free: yes materials analysis ds1743-100 buy mod;28 pin;600 dwg: 56-g0002-001a (pdf) use pkgcode/vari ation: mdf28-2 * 0c to +70c rohs/lead-free: no materials analysis ds1743-100+ sample buy mod;28 pin;600 dwg: 56-g0002-001a (pdf) use pkgcode/vari ation: mdf28+2 * 0c to +70c rohs/lead-free: yes materials analysis ds1743w-120 buy mod;28 pin;600 dwg: 56-g0002-001a (pdf) use pkgcode/vari ation: mdf28-2 * 0c to +70c rohs/lead-free: no materials analysis ds1743w-150 buy mod;28 pin;600 dwg: 56-g0002-001a (pdf) 0c to +70c rohs/lead-free: no materials analysis pa g e 1 of 3 ds1743 - part number table - maxim/dallas 30-jul-2007 mhtml:file://c:\temp\m axm\ds1743-85ind+.mht
didn't find what you need? use pkgcode/vari ation: mdf28-2 * ds1743w-120+ sample buy mod;28 pin;600 dwg: 56-g0002-001a (pdf) use pkgcode/vari ation: mdf28+2 * 0c to +70c rohs/lead-free: yes materials analysis ds1743w-150+ sample buy mod;28 pin;600 dwg: 56-g0002-001a (pdf) use pkgcode/vari ation: mdf28+2 * 0c to +70c rohs/lead-free: yes materials analysis ds1743w-120ind+ buy mod;28 pin;600 dwg: 56-g0002-001a (pdf) use pkgcode/vari ation: mdf28+2 * 0c to +70c rohs/lead-free: yes materials analysis ds1743w-120 ind buy mod;28 pin;600 dwg: 56-g0002-001a (pdf) use pkgcode/vari ation: mdf28-2 * -40c to +85c rohs/lead-free: no materials analysis ds1743-100 ind buy mod;28 pin;600 dwg: 56-g0002-001a (pdf) use pkgcode/vari ation: mdf28-2 * -40c to +85c rohs/lead-free: no materials analysis ds1743-100ind+ buy mod;28 pin;600 dwg: 56-g0002-001a (pdf) use pkgcode/vari ation: mdf28+2 * -40c to +85c rohs/lead-free: yes materials analysis ds1743wp-120ind+ buy pwrcp;34 pin;960 dwg: 56-g0003-001a1 (pdf) use pkgcode/vari ation: pc1+2 * -40c to +85c rohs/lead-free: yes materials analysis ds1743wp-120+ sample buy pwrcp;34 pin;960 dwg: 56-g0003-001a1 (pdf) use pkgcode/vari ation: pc1+2 * 0c to +70c rohs/lead-free: yes materials analysis ds1743wp-150 buy pwrcp;34 pin;960 dwg: 56-g0003-001a1 (pdf) use pkgcode/vari ation: pc1-2 * 0c to +70c rohs/lead-free: no materials analysis ds1743wp-120 buy pwrcp;34 pin;960 dwg: 56-g0003-001a1 (pdf) use pkgcode/vari ation: pc1-2 * 0c to +70c rohs/lead-free: no materials analysis ds1743wp-150+ sample buy pwrcp;34 pin;960 dwg: 56-g0003-001a1 (pdf) use pkgcode/vari ation: pc1+2 * 0c to +70c rohs/lead-free: yes materials analysis ds1743wp-120ind buy pwrcp;34 pin;960 dwg: 56-g0003-001a1 (pdf) use pkgcode/vari ation: pc1-2 * -40c to +85c rohs/lead-free: no materials analysis contact us: feedback, questions rate this page mail this page copyright ? 2007 by maxim integrated products, dallas semiconductor ? legal notices ? privacy policy pa g e 2 of 3 ds1743 - part number table - maxim/dallas 30-jul-2007 mhtml:file://c:\temp\m axm\ds1743-85ind+.mht
pa g e 3 of 3 ds1743 - part number table - maxim/dallas 30-jul-2007 mhtml:file://c:\temp\m axm\ds1743-85ind+.mht
ds1743p part number table english ? ? ?Z ? ??? what's new products solutions design appnotes support buy company members notes: 1. see the ds1743p quickview data sheet for further information on this product family or download the ds1743p full data sheet (pdf, 316kb). 2. other options and links for pu rchasing parts are listed at: http://www.maxim-ic.com/sales . 3. didn't find what you need? ask our applications engineers. expert assistance in finding parts, usually within one business day. 4. part number suffixes: t or t&r = tape and reel; + = rohs/lead-free ; # = rohs/lead-exempt. more: see full data sheet or part naming conventions . 5. * some packages have variations, list ed on the drawing. "pkgcode/variati on" tells which variation the product uses. part number free sample buy direct package: type pins size drawing code/var * temp rohs/lead-free? materials analysis ds1743p-c01+ buy pwrcp;34 pin;960 dwg: 56-g0003-001a1 (pdf) use pkgcode/vari ation: pc1+2 * 0c to +70c rohs/lead-free: yes materials analysis ds1743p-85+ sample buy pwrcp;34 pin;960 dwg: 56-g0003-001a1 (pdf) use pkgcode/vari ation: pc1+2 * 0c to +70c rohs/lead-free: yes materials analysis DS1743P-85IND+ buy pwrcp;34 pin;960 dwg: 56-g0003-001a1 (pdf) use pkgcode/vari ation: pc1+2 * -40c to +85c rohs/lead-free: yes materials analysis ds1743p-100 buy pwrcp;34 pin;960 dwg: 56-g0003-001a1 (pdf) use pkgcode/vari ation: pc1-2 * 0c to +70c rohs/lead-free: no materials analysis ds1743p-100ind buy pwrcp;34 pin;960 dwg: 56-g0003-001a1 (pdf) use pkgcode/vari ation: pc1-2 * 0c to +70c rohs/lead-free: no materials analysis ds1743p-100ind+ buy pwrcp;34 pin;960 dwg: 56-g0003-001a1 (pdf) 0c to +70c rohs/lead-free: yes pa g e 1 of 2 ds1743p - part number table - maxim/dallas 30-jul-2007 mhtml:file://c:\temp\m axm\DS1743P-85IND+.mht
didn't find what you need? use pkgcode/vari ation: pc1+2 * materials analysis ds1743p-100+ sample buy pwrcp;34 pin;960 dwg: 56-g0003-001a1 (pdf) use pkgcode/vari ation: pc1+2 * 0c to +70c rohs/lead-free: yes materials analysis contact us: feedback, questions rate this page mail this page copyright ? 2007 by maxim integrated products, dallas semiconductor ? legal notices ? privacy policy pa g e 2 of 2 ds1743p - part number table - maxim/dallas 30-jul-2007 mhtml:file://c:\temp\m axm\DS1743P-85IND+.mht

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